The Design of Improved Dynamic AES and Hardware Implementation Using FPGA

ByteSub is a key module in the AES hardware architectures. Most of the ByteSub design is accomplished by look-up table method. To reduce the complexity of AES module and improve the performance and security, we propose a novel dynamic ByteSub generator, which is composed of finite field inverse and multipliers. In our design, look-up table method is no more essential to the ByteSub hardware architecture. The proposed design is implemented on Altera APEX20KE FPGA family of devices. It needs 44218 logic cell elements on FPGA chip and the performance can be achieve to 57.2 MHz. Our proposed design does not need any memory elements.